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QC2.0 test

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发表于: 20-04-2018 10:59:56
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Edited by xbj20090320 at 20-04-2018 11:03

Hi
  I just got a CT-2,when i test it ,i found the profile couldn't meet the qc2.0 standard completely.according the qc2.0,the D+=D-=0.6 more than 1s ,the D-=0.then the HVDCP is ready to accept the request.but as the below photo,the D-level always kept at 0v. why? thank!

Capture11.PNG
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 楼主| 发表于: 20-04-2018 11:06:06
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Edited by xbj20090320 at 20-04-2018 11:07

the QC2.0 Standard profile looks like this.
Capture12.PNG
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发表于: 21-04-2018 00:44:57
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Thanks for your feedback.

First I want to say that when CT-2 is developed, there're no much documentation, all we can do is trying to reverse-engineer how it works. Even now, I can only see a little documentation, in some datasheets of chips with HVDCP supported. I guess the HVDCP standard is still not public, your pictures seems directly released from Qualcomm.

As far as I know (Tell me if my statements went wrong), HVDCP hosts should first support DCP, which means that at the initial state, the host should SHORT D+ and D-, this means when you apply a voltage on D+, and if the charger is HVDCP supported, the same voltage should be on D-. Actually I verified this on a lot of chargers, they all have a short on D+ and D- initially. So I guess you didn't get this result on a charger which is not HVDCP supported.

Please tell me if this procedure isn't standard.
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